Will Conley, Cymer, USA
Jae Won Hahn, Yonsei University, South Korea
The successful integration of design, layout, imaging solutions and advances in process technologies continue to provide viable working solutions to continue the advancement of Logic and Memory technologies. This topical review will highlight recent advances in design layout to on wafer imaging to on wafer final etch of circuitry. Areas of interest include layout ground rules, use of machine learning throughout the design, verification cycle and the application to imaging solutions through pupil and mask optimization (SMO). Insight into metrology issues, Scanner/source (laser) improvements and the integration of etch processes will be reviewed.